IRFL9014, sihfl9014 www.vishay.com vishay siliconix s13-0170-rev. e, 04-feb-13 1 document number: 91195 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power mosfet features ? surface mount ? available in tape and reel ? dynamic dv/dt rating ? repetitive avalanche rated ?p-channel ? fast switching ? ease of paralleling ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 description third generation power mosfets from vishay provide the designer with the best combi nation of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. the sot-223 package is designed for surface-mounting using vapor phase, infrared, or wave soldering techniques. its unique package design allows for easy automatic pick-and-place as with other sot or soic packages but has the added advantage of improved therma l performace due to an enlarged tab for he atsinking. power dissipation of greater than 1.25 w is possi ble in a typical surface mount application. note a. see device orientation. notes a. repetitive rating; pu lse width limited by maximum junction temperature (see fig. 11). b. v dd = - 25 v, starting t j = 25 c, l = 50 mh, r g = 25 ? , i as = - 1.8 a (see fig. 12). c. i sd ? - 6.7 a, di/dt ? 90 a/s, v dd ? v ds , t j ? 150 c. d. 1.6 mm from case. e. when mounted on 1" square pcb (fr-4 or g- 10 material). product summary v ds (v) - 60 r ds(on) ( ? )v gs = - 10 v 0.50 q g (max.) (nc) 12 q gs (nc) 3.8 q gd (nc) 5.1 configuration single s g d p-channel mosfet sot-223 g d s d ordering information package sot-223 sot-223 lead (pb)-free and halogen- free sihfl9014-ge 3 sihfl9014tr-ge3 lead (pb)-free IRFL9014pbf IRFL9014trpbf a sihfl9014-e3 sihfl9014t-e3 a absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds - 60 v gate-source voltage v gs 20 continuous drain current v gs at - 10 v t c = 25 c i d - 1.8 a t c = 100 c - 1.1 pulsed drain current a i dm - 14 linear dera ting factor 0.025 w/c linear derating fa ctor (pcb mount) e 0.017 single pulse avalanche energy b e as 140 mj repetitive avalanche current a i ar - 1.8 a repetitive avalanche energy a e ar 0.31 mj maximum power dissipation t c = 25 c p d 3.1 w maximum power dissipation (pcb mount) e t a = 25 c 2.0 peak diode recovery dv/dt c dv/dt - 4.5 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (peak temperature) d for 10 s 300
IRFL9014, sihfl9014 www.vishay.com vishay siliconix s13-0170-rev. e, 04-feb-13 2 document number: 91195 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note a. when mounted on 1" square pcb (fr-4 or g- 10 material). notes a. repetitive rating; pu lse width limited by maximum junction temperature (see fig. 11). b. pulse width ? 300 s; duty cycle ? 2 %. thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient (pcb mount) a r thja -60 c/w maximum junction-to-case (drain) r thjc -40 specifications (t j = 25 c, unless otherwise noted) parameter symbol test condi tions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a - 60 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = 1 ma - - 0.059 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a - 2.0 - - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = - 60 v, v gs = 0 v - - - 100 a v ds = - 48 v, v gs = 0 v, t j = 125 c - - - 500 drain-source on-state resistance r ds(on) v gs = - 10 v i d = 1.1 a b - - 0.50 ? forward transconductance g fs v ds = - 25 v, i d = 1.1 a b 1.3 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 270 - pf output capacitance c oss - 170 - reverse transfer capacitance c rss -31- total gate charge q g v gs = - 10 v i d = - 6.7 a, v ds = - 48 v, see fig. 6 and 13 b --12 nc gate-source charge q gs --3.8 gate-drain charge q gd --5.1 turn-on delay time t d(on) v dd = - 30 v, i d = - 6.7 a, r g = 24 ? , r d = 4.0 ? , see fig. 10 b -11- ns rise time t r -63- turn-off delay time t d(off) -9.6- fall time t f -31- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact -4.0- nh internal source inductance l s -6.0- drain-source body diode characteristics continuous source-dra in diode current i s mosfet symbol showing the integral reverse p - n junction diode --- 1.8 a pulsed diode forward current a i sm --- 14 body diode voltage v sd t j = 25 c, i s = - 1.8 a, v gs = 0 v b --- 5.5v body diode reverse recovery time t rr t j = 25 c, i f = - 6.7 a, di/dt = 100 a/s b - 80 160 ns body diode reverse recovery charge q rr - 0.096 0.19 c forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) d s g s d g
IRFL9014, sihfl9014 www.vishay.com vishay siliconix s13-0170-rev. e, 04-feb-13 3 document number: 91195 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics, t c = 25 c fig. 2 - typical output characteristics, t c = 150 c fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage 20 s pulse width t c = 25 c 4.5 v bottom to p v gs - 15 v -10 v -8.0 v -7.0 v -6.0 v -5.5 v -5.0 v -4.5 v 91195_01 - v ds , drain-to-source voltage (v) - i d , drain current (a) 10 1 10 0 10 -1 10 0 10 1 10 -1 91195_02 4.5 v bottom to p v gs - 15 v -10 v -8.0 v -7.0 v -6.0 v -5.5 v -5.0 v -4.5 v 10 1 10 0 10 0 10 1 10 -1 - v ds , drain-to-source voltage (v) - i d , drain current (a) 20 s pulse width t c = 150 c 91195_03 25 c 150 c 20 s pulse width v ds = - 25 v 10 1 10 0 - i d , drain current (a) - v gs , gate-to-source voltage (v) 5678910 4 10 -1 91195_04 i d = - 6.7 a v gs = 10 v 0.0 0.5 1.0 1.5 2.0 2.5 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( c) r ds(on) , drain-to-source on resistance (normalized) 91195_05 600 500 400 300 0 100 200 10 0 10 1 capacitance (pf) - v ds , drain-to-source voltage (v) c iss c rss c oss v gs = 0 v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 91195_06 i d = -6.7 a v ds = -48 v for test circuit see figure 13 v ds = -30 v q g , total gate charge (nc) - v gs , gate-to-source voltage (v) 20 16 12 8 0 4 0 416 12 8
IRFL9014, sihfl9014 www.vishay.com vishay siliconix s13-0170-rev. e, 04-feb-13 4 document number: 91195 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 7 - typical source-dr ain diode forward voltage fig. 8 - maximum safe operating area fig. 9 - maximum drain curre nt vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case 91195_07 10 1 10 0 - v sd , source-to-drain voltage (v) - i sd , reverse drain current (a) 1.0 5.0 4.0 3.0 2.0 25 c 150 c v gs = 0 v 6.0 10 -1 91195_08 100 s 1 ms 10 ms operation in this area limited by r ds(on) t c = 25 c t j = 150 c single pulse - i d , drain current (a) 10 2 2 5 2 5 2 5 - v ds , drain-to-source voltage (v) 1 10 10 2 25 25 2 5 0.1 1 10 0.1 25 10 3 91195_09 - i d , drain current (a) t c , case temperature (c) 0.0 0.5 1.0 1.5 2.0 25 150 125 100 75 50 pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. - 10 v + - v ds v dd v gs 10 % 90 % v ds t d(on) t r t d(off) t f 91195_11 0 ? 0.5 0.2 0.1 0.05 0.01 single pulse (thermal response) p dm t 1 t 2 notes: 1. duty factor, d = t 1 /t 2 2. peak t j = p dm x z thjc + t c 0.02 thermal response (z ? jc ) 1 0.1 10 -2 t 1 , rectangular pulse duration (s) 10 -5 10 -4 10 -3 10 -2 0.1 1 10 10 2 10 10 2 10 3
IRFL9014, sihfl9014 www.vishay.com vishay siliconix s13-0170-rev. e, 04-feb-13 5 document number: 91195 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit r g i as 0.01 t p d.u.t l v ds + - v dd - 10 v var y t p to obtain required i as i as v ds v dd v ds t p 91195_12c bottom to p i d - 0.80 a - 1.1 a - 1.8 a v dd = - 25 v 400 0 100 200 300 25 150 125 100 75 50 starting t j , junction temperature (c) e as , single pulse energy (mj) q gs q gd q g v g charge - 10 v d.u.t. - 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
IRFL9014, sihfl9014 www.vishay.com vishay siliconix s13-0170-rev. e, 04-feb-13 6 document number: 91195 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 14 - for p-channel vishay siliconix maintains worldwide manufactu ring capability. products may be manufact ured at one of seve ral qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91195 . p.w. period di/dt diode recovery dv/dt body diode forward drop body diode forward current driver gate drive inductor current d = p.w. period + - - - - + + + peak dio d e recovery d v/ d t test circuit ? dv/dt controlled by r g ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low stray inductance ? g round plane ? low leakage inductance current tran s former r g ? compliment n-channel of d.u.t. for driver v dd ? i s d controlled by duty factor d note note a. v gs = - 5 v for logic level and - 3 v drive device s v gs = - 10 v a d.u.t. l s d waveform d.u.t. v d s waveform v dd re-applied voltage ripple 5 % i s d rever s e recovery current
document number: 91363 www.vishay.com revision: 15-sep-08 1 package information vishay siliconix sot-223 (high voltage) notes 1. dimensioning and toler ancing per asme y14.5m-1994. 2. dimensions are shown in millimeters (inches). 3. dimension do not include mold flash. 4. outline conforms to jedec outline to-261aa. d b 3 b1 0.10 (0.004) m c m h 0.10 (0.004) m c b m 0.20 (0.00 8 ) m c a m 0.10 (0.004) m c b m 3 x b e1 e 1 2 3 a e 4 c a 0.0 8 (0.003) 4 x l l1 4 x c 3 millimeters inches dim. min. max. min. max. a 1.55 1.80 0.061 0.071 b 0.65 0.85 0.026 0.033 b1 2.95 3.15 0.116 0.124 c 0.25 0.35 0.010 0.014 d 6.30 6.70 0.248 0.264 e 3.30 3.70 0.130 0.146 e 2.30 bsc 0.0905 bsc e1 4.60 bsc 0.181 bsc h 6.71 7.29 0.264 0.287 l 0.91 - 0.036 - l1 0.061 bsc 0.0024 bsc - 10' - 10' ecn: s-82109-rev. a, 15-sep-08 dwg: 5969
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